Document Type
Postprint
Publication Date
11-2004
Publication Title
IEEE Journal on Solid State Circuits
Publisher
IEEE
Volume
39
Issue
11
First page number:
1819
Last page number:
1828
Abstract
This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator's critical performance specifications are derived from the CDMA receiver specifications.
Keywords
Analog–digital conversion; Analog-to-digital converters; CMOS; Code division multiple access (CDMA); Continuous-time delta-sigma modulation; High-speed integrated circuit; Integrated circuits; Metal oxide semiconductors; Complementary; Modulators (Electronics)
Repository Citation
Dagher, E. H.,
Stubberud, P.,
Masenten, W. K.,
Conta, M.,
Dinh, T. V.
(2004).
A 2 GHz Bandpass Analog to Digital Delta-sigma Modulator for CDMA Receivers with 79 DB Dynamic Range in 1.23 MHz Bandwidth.
IEEE Journal on Solid State Circuits, 39(11),
1819-1828.
IEEE.
https://digitalscholarship.unlv.edu/ece_fac_articles/143
Comments
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