Award Date

8-1-2016

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

Russel J. Baker

Second Committee Member

Yahia Baghzouz

Third Committee Member

Evangelos Yfantis

Fourth Committee Member

Peter A. Stubberud

Number of Pages

166

Abstract

Analog-to-digital converters are critically important in electronic systems. The

difficulty in meeting high performance parameters increases as integrated circuit design

process technologies advance into the deep nanometer region. Sigma-delta analog-todigital

converters are an attractive option to fulfill many data converter requirements.

These data converters offer high performance while relaxing requirements on the precision

of components within an integrated circuit. Despite this, the active integrators found within

sigma-delta analog-to-digital converters present two main challenges. These challenges are

the power consumption of the active amplifier and achieving gain-bandwidth necessary for

sigma-delta data converters in deep nanometer process technologies. Both of these

challenges can be resolved through the replacement of active integrators with passive

integrators at the expense of resolution.

Three passive sigma-delta topologies were examined and characterized in detail.

Two of these topologies were first-order and second-order noise shaping topologies. A new

passive topology was developed which was determined to be optimal in resolution

compared to the two traditional designs. This topology exhibits a first-order signal transfer

function and a second-order noise transfer function. A method for increasing resolution of

passive sigma-delta data converters despite inherent performance constraints was

developed.

Three example circuits were designed, fabricated and tested using On

Semiconductor’s C5 500 nanometer CMOS process. These designs were optimized for low

power and utilized memory sense amplifiers as quantizing elements. The first circuit, using

passive lumped on-chip elements for the noise shaping network achieved a power

consumption of 100 micro-watts and an effective resolution of 8-bits. The second circuit

replaced the lumped components with switched-capacitor elements and achieved a power

consumption of 6.75 micro-watts and an effective resolution of 9.3 bits. The third circuit

was designed as a case study for the application of the proposed topology to “K-delta-1-

sigma” modulators. This circuit achieved a power consumption of 10 milli-watts and an

effective resolution of 8.5 bits.

Keywords

Analog; CMOS; Digital; Integrated Circuit; Mixed Signal; Semiconductor

Disciplines

Computer Engineering | Electrical and Computer Engineering | Nanoscience and Nanotechnology

File Format

pdf

Degree Grantor

University of Nevada, Las Vegas

Language

English

Rights

IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

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