Award Date

12-2010

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

Henry Selvaraj, Chair

Second Committee Member

Shahram Latifi

Third Committee Member

Emma E. Regentova

Graduate Faculty Representative

Lawrence L. Larmore

Number of Pages

80

Abstract

A Deadlock-free routing algorithm can be generated for arbitrary interconnection network using the concept of virtual channels but the virtual channels will lead to more complex algorithms and more demands of NOC resource.


In this thesis, we study a Torus topology for NOC application, design its structure and propose a routing algorithm exploiting the characteristics of NOC. We have chosen a typical 16 (4 by 4) routers Torus and propose the corresponding route algorithm. In our algorithm, all the channels are assigned 4 different dimensions (n0,n1,n2 & n3). By following the dimension increment method, we break the dependent route circles, and avoid dead lock and live-lock and avoid the overhead of virtual channels.


Xilinx offers two soft core processors, namely Picoblaze and Microblaze. The Picoblaze processor is 8-bit configurable processor core. These soft processor cores offer designers tremendous flexibility during the design process, allowing the designers to configure the processor to meet the needs of their systems (e.g., adding custom instructions or including/excluding particular data path coprocessors) and to quickly integrate the processor within any FPGA. Unlike single chip Microprocessor/FPGA systems using hard-core processors, soft processor cores allow designers to incorporate varying numbers of processors within a single FPGA design depending on an application’s needs.

Soft processor cores implemented using FPGAs typically have higher power consumption and decreased performance compared with hard-core processors. Key features of the Picoblaze processor, as well as other soft processor cores, include the user configurable options that allow a designer to tailor the processor’s functionality to their specific design.


The proposed design implements sixteen instances of a soft processor, Picoblaze, connected in a torus topology. Data is passed from one processor to another employing a routing algorithm which is based on dimension increment method. Thus we design an NOC with multiple microcontrollers and related logic, synthesize the process and test its performance in a simulation environment.

Keywords

Deadlocks; Livelock; Microcontroller; Microprocessors; Networks on a chip; NOC; Picoblaze; Routing protocols (Computer network protocols); Torus

Disciplines

Computer and Systems Architecture | Computer Engineering | Electrical and Computer Engineering | Hardware Systems | Signal Processing | Systems and Communications

File Format

pdf

Degree Grantor

University of Nevada, Las Vegas

Language

English

Rights

IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

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