Location
UNLV SEB Lobby & Auditorium
Start Date
26-4-2013 9:30 AM
End Date
26-4-2013 3:00 PM
Description
Implementing image processing algorithms on FPGA has recently become more popular since it provides high speed in comparison with software-based approaches. In this paper, we have presented fast pipeline-based architecture for one of the most popular edge detection algorithms called Sobel edge detection. The objective of our work is to present two fast pipeline-based architectures for Sobel edge detection on FPGA benefiting one and two way parallelism. We used Verilog language to implement our designs and we synthesized each one for Cyclone IV FPGA. Experimental results show that our pipeline-based architectures perform edge detection process more than 379 and 751 times faster than software-based approach using MATLAB.
Keywords
Computer algorithms; Computer architecture; Field programmable gate arrays; Image processing – Digital techniques
Disciplines
Computer Sciences | Theory and Algorithms
Language
English
Fast Sobel Edge Detection Using Parallel Pipeline-based Architecture on FPGA
UNLV SEB Lobby & Auditorium
Implementing image processing algorithms on FPGA has recently become more popular since it provides high speed in comparison with software-based approaches. In this paper, we have presented fast pipeline-based architecture for one of the most popular edge detection algorithms called Sobel edge detection. The objective of our work is to present two fast pipeline-based architectures for Sobel edge detection on FPGA benefiting one and two way parallelism. We used Verilog language to implement our designs and we synthesized each one for Cyclone IV FPGA. Experimental results show that our pipeline-based architectures perform edge detection process more than 379 and 751 times faster than software-based approach using MATLAB.