Hardware Implementation of Processor Allocation Schemes for Mesh-based Chip Multiprocessors

Document Type

Article

Publication Date

2-2010

Publication Title

Microprocessors and Microsystems

Volume

34

Issue

1

First page number:

39

Last page number:

48

Abstract

Well-designed Processor Allocator (PA) is an important factor in modern Chip MultiProcessors (CMPs). It needs to be fast as well as area and energy efficient, because it is only a small component of the CMP. In this paper, we propose an architecture for such an efficient and fast PA. The PA structure is based on bit map approach and is driven by an Improved First Fit (IFF) algorithm, which is presented and described. Together with the proposed IFF technique, a new Improved Adaptive Scan (IAS) and an Improved Quick Allocation (IQA) algorithms are introduced and discussed and compared with previously known important techniques. The presented synthesis results reveal that the proposed PA achieves good frequency results while, at the same time is characterized by low logic utilization.

Keywords

Algorithms--Data processing; Commuting--Energy consumption; Computer architecture; Microprocessors; Networks on a chip; Parallel computers

Disciplines

Computer and Systems Architecture | Computer Engineering | Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Hardware Systems | Power and Energy | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited

UNLV article access

Search your library

Share

COinS