An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA Devices

Document Type

Article

Publication Date

6-2005

Publication Title

Journal of Systems Architecture

Volume

51

Issue

6-7

First page number:

424

Last page number:

434

Abstract

Modern FPLD devices have very complex structure. They combine PLA like structures, as well as FPGA and even memory-based structures. However lack of appropriate synthesis methods do not allow fully exploiting the possibilities the modern FPLDs offer. The paper presents a general method for the synthesis targeted to implementation of sequential circuits using embedded memory blocks. The method is based on the serial decomposition concept and relies on decomposing the memory block into two blocks: a combinational address modifier and a smaller memory block. An appropriately chosen decomposition strategy may allow reducing the required memory size at the cost of additional logic cells for address modifier implementation. This makes possible implementation of FSMs that exceed available memory by using embedded memory blocks and additional programmable logic.

Keywords

Computer algorithms; Decomposition method; Field programmable gate arrays; Gate array circuits; Sequential machine theory

Disciplines

Computer Engineering | Digital Circuits | Electrical and Computer Engineering | Electrical and Electronics | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited

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