Scalable and Fault-tolerant network-on-chip Design Using the Quartered Recursive Diagonal Torus Topology

Authors

Xianfang Tan, University of Nevada, Las VegasFollow
Lei Zhang, University of Nevada, Las VegasFollow
Shankar Neelkrishnan, University of Nevada, Las VegasFollow
Mei Yang, University of Nevada, Las VegasFollow
Yingtao Jiang, University of Nevada, Las VegasFollow
Yulu Yang, University of Nevada, Las VegasFollow

Document Type

Conference Proceeding

Publication Date

2008

Publication Title

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Publisher

Sherpa-Romeo

First page number:

309

Last page number:

314

Abstract

Network-on-a-chip (NoC) is an effective approach to connect and manage the communication between the variety of design elements and intellectual property blocks required in large and complex system-on-chips. In this paper, we propose a new NoC architecture, referred as the Quartered Recursive Diagonal Torus (QRDT), which is constructed by overlaying diagonal torus. Due to its small diameter and rich routing recourses, QRDT is determined to be well suitable to construct highly scalable NoCs.

In QRDT, data packets can be routed through a proposed minimal routing algorithm based on the Johnson codes that have traditionally been used in finite state machine designs. It has been shown that this proposed routing algorithm with minor modifications is capable of handling the single link/node failure. The hardware cost of the proposed QRDT architecture and its associated routing algorithm is revealed by designing two QRDT routers which have been synthesized using TSMC 0.18¼m CMOS technology.

Disciplines

Electrical and Computer Engineering | Engineering

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

Repository Citation

Tan, X., Zhang, L., Neelkrishnan, S., Yang, M., Jiang, Y., Yang, Y. (2008). Scalable and Fault-tolerant network-on-chip Design Using the Quartered Recursive Diagonal Torus Topology. Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 309-314. Sherpa-Romeo.