Award Date

1-1-2006

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical and Computer Engineering

First Committee Member

Henry Selvaraj

Number of Pages

70

Abstract

In recent years Programmable Logic Devices (PLD) and in particular Field Programmable Gate Arrays (FPGAs) have seen a tremendous increase in sales and applications in the area of embedded systems. The main advantage of FPGAs is the flexibility that they offer a designer in reconfiguring the hardware. The flexibility achieved through re-configuration of FPGAs usually incurs an overhead of extra execution time, data memory and also power dissipation; FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream generation process for FPGAs become available, JBits is one of them. With run-time reconfiguration of FPGAs, we can perform partial reconfiguration, which allows reconfiguration of a part of an FPGA while the other part is executing some functional computation. The partial reconfiguration of a function can be performed earlier than the time when the function is really needed. Such configuration pre-fetch can hide the reconfiguration overhead more effectively; This thesis will implement a reconfigurable system and study the effect of runtime reconfiguration using VERILOG and a new Java based tool JBITS. This work will provide pointers to high level synthesis tools targeting runtime re-configuration.

Keywords

Analysis; Configuration; Runtime; System

Controlled Subject

Electrical engineering

File Format

pdf

File Size

2263.04 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

Permissions

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Identifier

https://doi.org/10.25669/x09a-y9cb


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