Design and Analysis of First and Second Order K-~Delta-~1-~Sigma Modulators in Multiple Fabrication Processes
Analog to digital converters (ADC) are an important category of electronic circuits that are required in order to convert real-world analog signals into the digital domain. One of the main trade-offs in ADC design is between data conversion speed and resolution. Delta Sigma ADCs are commonly used for high precision data conversion of low bandwidth signals such as those found in audio, industrial and biomedical applications. A major disadvantage of traditional Delta Sigma ADC architectures is that they have limited signal bandwidth and are not suited for high speed applications such as communication systems. The continuous time K-Delta-1-Sigma (KD1S) modulator designed and implemented in this thesis offers a solution to this problem by using time interleaving with and multiple feedback paths to increase the effective sampling rate.
Four different 1st and 2nd order continuous time KD1S modulators were extensively designed and simulated. These KD1S modulators were implemented in two different processes, a 0.5 μm CMOS process and a 0.35 μm SiGe BiCMOS process. All designs utilize 8 feedback paths (delta) and therefore have the required 8 phase shifted clocks. The main parameters that were simulated are signal-to-noise ratio (SNR), effective number of bits (ENOB), bandwidth and power consumption. These simulations were performed using a combination of LTSpice, and MATLAB. Overall, the 2nd order KD1S modulators have better performance than the 1st order designs across both processes.
The 2nd order KD1S modulator implemented in the 0.35 μm process has the best performance and was physically laid out using the Cadence Virtuoso suite. This design had an SNR of 76.73 dB with a 500 KHz input signal, which corresponds to an ENOB of 12.45 bits. This resolution was achieved with a bandwidth of 1.92 MHz and an effective sampling rate of 983 MHz with a power consumption of 35.7 mW.