Award Date


Degree Type


Degree Name

Master of Science in Electrical Engineering (MSEE)


Electrical and Computer Engineering

First Committee Member

R. Jacob Baker

Second Committee Member

Robert Schill

Third Committee Member

Biswajit Das

Fourth Committee Member

Monika Neda

Number of Pages



The design, simulation, fabrication, and testing of a 6-bit current-mode ADC is presented with related calculations. Capable of producing samples at greater than 100MHz, the proposed design should excel at measuring fast current transients such as those produced by arrays of avalanche photodiodes (APDs). An array of 63 current comparators feed digital logic gates, via “thermometer code,” that produce a 6-bit output word that is driven off-chip by appropriate buffers.The circuit was designed using Cadence Virtuoso design software. Simulated Differential Non-Linearity (DNL), with an 8µA reference current, is 1.656 LSB at the worst transition involving a scale change. Excluding scale changes (where different current mirror sizes are used for different sections of the input range) the worst DNL is 0.229 LSB. Worst Integral Non-Linearity (INL) is -2.29 LSB. Simulations indicate delay for digital logic to encode results from comparators into a 6-bit word is less than 1ns. Output buffers are designed to drive 10pF load capacitance at a frequency of at least 100MHz. Fabrication was in a 180nm SiGe BiCMOS process. The complete design is 830µm x 395µm for a layout area of 0.328mm2. Layout techniques and strategy are described, including isolation structures, power delivery, and standard cells for digital design. Metal routing and shielding techniques are described. Integration with a test Printed Circuit Board (PCB) is described. The ADC is characterized and test results are presented. Oscilloscope measurements indicate buffers are capable of driving signals at frequencies in excess of 100MHz. The complete system power consumption can exceed 50mW. Conditions that affect power consumption are investigated. Methods to stabilize power delivery and associated challenges are described as well as possible future design mitigations. The proposed ADC is demonstrated to have a response sufficient for high-speed operation.


Analog CMOS; Avalanche photo diode; Current Comparator; Standard cell layout


Electrical and Computer Engineering

File Format


File Size

9700 KB

Degree Grantor

University of Nevada, Las Vegas




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