Award Date

May 2023

Degree Type


Degree Name

Master of Science in Engineering (MSE)


Electrical and Computer Engineering

First Committee Member

R. Jacob Baker

Second Committee Member

Emma Regentova

Third Committee Member

Peter Stubberud

Fourth Committee Member

Mohamed Kaseko

Number of Pages



This thesis first aims to understand how a part of the computed tomography (CT) algorithm called “forward projector” (FP) works and how it can be accelerated at a hardware level. Two methods of FP are defined and studied: pixel-driven and ray-driven. Both methods fundamentally use the property of line integral and Bresenham’s algorithm. As the result of the study of the two FP methods, the ray-driven algorithm implemented in C++ performed 35% faster than the pixe-driven algorithm implemented in Python.This thesis implements the ray-driven forward projector algorithm using field-programmable gate array (FPGA), making use of hardware-acceleration techniques. The result shows that the FPGA implementation had a comparable speed advantage compared to the implementation on the personal computer (PC). Even though the FPGA used was outdated and budget-oriented, the chip was able to perform 58% of the performance of a more expensive, modern, and performance-oriented PC. Also, the FPGA implementation performed better in power consumption compared to the PC. Methodologies included the state machine, random access memory (RAM), and universal asynchronous receiver-transmitter (UART). By using the results in this thesis, a CT scanner can be designed to be less expensive, more efficient, faster, and use less power.


Investigative Techniques

Degree Grantor

University of Nevada, Las Vegas




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