Award Date


Degree Type


Degree Name

Master of Science (MS)


Electrical and Computer Engineering

First Committee Member

Yingtao Jiang

Number of Pages



The first objective of this research project was to evaluate the performance of various logic block architectures in FPGAs. Since logic blocks widely vary in size, functionality and complexity, we were motivated to explore them in detail. For our study, logic blocks from Actel, Altera, Quicklogic and Xilinx were chosen along with some designs discussed in the academia. These cells were either multiplexer based or look-up-table (LUT) based. Structural VHDL models of all these blocks were constructed and benchmarks circuits were mapped. Results at this stage suggested that, although the coarse grained cells occupied more area and showed poor utilization, they were considerably faster than the fine grained cells; The second objective was to improve the performance of the Actel Proasicplus (fine grained) logic block by enhancing its functional capabilities. During this process we came up with three modified architectures. These new cells were laid out in MAGIC using a TSMC 0.18mum technology file with lambda = 0.09 mum and the extracted files were simulated in PSpice. This transistor level data helped us to estimate the area and propagation delay of the new architectures. The modified architectures were also tested for performance by implementing the previous benchmarks and a significant improvement in speed, occupied area and utilization was observed.


Analysis; Architectures; Block; Cells; Fine; Functional; Grained; Improvement; Logic

Controlled Subject

Electrical engineering

File Format


File Size

3645.44 KB

Degree Grantor

University of Nevada, Las Vegas




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