Award Date

December 2018

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

R. J. Baker

Second Committee Member

Biswajit Das

Third Committee Member

Emma Regentova

Fourth Committee Member

Kathleen Robins

Number of Pages

67

Abstract

As the electronics industry moves forward there is an increasing need to process information faster and more accurately. High speed signals are used in scientific instrumentation, range finding devices, radar applications, and electro-optical interfaces. High-speed state of the art analog-to-digital converters are required to process these signals in real time. High frequency signals or very fast pulses are not able to be processed accurately due to either Nyquist-rate limitations or practical power consumption limits. For applications where signals are transient in nature and design size and power consumption are major factors, the proposed Variable Fast Transient Digitizer (VFTD) will be able to discretize fast signals and reproduce them with minimal signal loss. The VFTD can be coupled with micro-controllers to process these very fast signals and pulses that operate in the gigahertz (GHz) range, while minimizing static power consumption and package size [1].

The VFTD designed is an application specific integrated circuit (ASIC) that can capture and store a high-speed analog input signal at a variable rate. The stored signal can be replicated at a slower rate, also adjustable, for user specific applications. The reconstruction process is adjustable to allow for interfacing with different microprocessors that vary across a range of operating frequencies and costs. This implementation of the VFTD utilizes 256 on-chip capacitors to store the data. Experimental results show the fastest rate of capture to be roughly 3.16 GHz, or 316 ps per stage, with slower rates of capture dependent upon off-chip bias resistors values. The capture rate and number of stages determine the overall capture window. For example, with 256 stages and 316 ps per stage the total capture window is roughly 81 ns, and with 6.25 ns per stage the capture window is roughly 1.59 us. The variable control and off-chip resistor allow for user and application specific modifications. The 256-stage VFTD can be implemented on a chip in a 0.5 mm x 1.5 mm area. The VFTD integrated circuit (IC) used for testing was fabricated by MOSIS using On Semiconductor's C5 Process.

Disciplines

Electrical and Computer Engineering

File Format

pdf

Degree Grantor

University of Nevada, Las Vegas

Language

English

Rights

IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

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