Award Date

December 2018

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

Russel J. Baker

Second Committee Member

Biswajit Das

Third Committee Member

Yingtao Jiang

Fourth Committee Member

Victor H. Kwong

Number of Pages

111

Abstract

In microelectronics, analog-to-digital converters (ADCs) are used as interfaces to convert analog inputs into discrete time or digital values that can be read via microcontrollers. As speed requirements and processing times in electronics continue to increase, high speed ADCs are increasingly critical components in the design of application-specific integrated circuits (ASICs). However, high speed ADCs introduce quantization error and are inefficient relative to size, cost, and power dissipation when compared to a High Speed Fast Transient Digitizer (HSFTD).

This thesis presents the design, layout, and simulation of a HSFTD designed to sample, in time at a fast rate, a high-speed analog input signal. The reconstructed, captured signal can then be readout at a much slower rate, for example, around three orders of magnitude. This approach eliminates quantization error in the captured signal and allows slow, low cost, analog-to-digital converters to be used such as those found in microcontrollers. The design uses four interleaved sampling banks, each containing 64 unit cells acting as sequentially triggered capture and hold stages with a typical maximum sampling frequency of 17.1 GHz. The capture stages are initiated via four trigger signals separated by a time delay equal to one-fourth of a unit cell propagation delay. The sampling rate can also be adjusted by tuning a bias generator's external control voltage or changing the value of an off-chip bias resistor. The effective sampling rate of 17.1 GHz results in data captured at 58 ps per unit cell with a minimum capture window of 15 ns for all 256 unit cells. The typical analog input voltage range is from 0 V to 2.2 V with an output range from 2 V to 4.8 V. At room temperature, the RMS value of the thermal noise in the design is limited by an 85.75 fF hold capacitor with kT/C noise resulting in a thermal noise floor of 220 μV,RMS. The amount of degradation of the unit cell hold capacitor's voltage over time due to leakage is 2.5 mV/100 μs.

Keywords

ADC; analog; ASIC; digitizer; sampling; Transient

Disciplines

Electrical and Computer Engineering

File Format

pdf

Degree Grantor

University of Nevada, Las Vegas

Language

English

Rights

IN COPYRIGHT. For more information about this rights statement, please visit http://rightsstatements.org/vocab/InC/1.0/

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